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| www..com Intel(R) Embedded Flash Memory (J3 v. D) (32, 64, and 128 Mbit) Datasheet Product Features Architecture -- High-density symmetrical 128-Kbyte blocks --128 Mbit (128 blocks) --64 Mbit (64 blocks) --32 Mbit (32 blocks) Performance -- 75 ns Initial Access Speed (128/64/32 -Mbit densities) -- 25 ns 8-word and 4-word Asynchronous page-mode reads -- 32-Byte Write buffer --4 s per Byte Effective programming time System Voltage and Power -- VCC = 2.7 V to 3.6 V -- VCCQ = 2.7 V to 3.6 V Security -- Enhanced security options for code protection -- 128-bit Protection Register --64-bit Unique device identifier --64-bit User-programmable OTP cells -- Absolute protection with V PEN = GND -- Individual block locking -- Block erase/program lockout during power transitions Software -- Program and erase suspend support -- Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Quality and Reliability -- Operating temperature: -40 C to +85 C -- 100K Minimum erase cycles per block -- 0.13 m ETOXTM VIII Process Packaging -- 56-Lead TSOP package -- 64-Ball Intel(R) Easy BGA package The Intel(R) Embedded Flash Memory J3 Version D (J3 v. D) provides improved mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel 0.13 m ETOXTM VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 v. D device brings reliable, low-voltage capability (3 V read, program, and erase) with high speed, low-power operation. The J3 v. D device takes advantage of the proven manufacturing experience and is ideal for code and data applications where high density and low cost are required, such as in networking, telecommunications, digital set top boxes, audio recording, and digital imaging. Intel Flash Memory components also deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel(R) Flash Memory devices. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 308551- 002 Sept 2005 www..com INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) Embedded Flash Memory (J3 v. D) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2005, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 2 Datasheet www..com Contents 1.0 Introduction .................................................................................................................. 6 1.1 1.2 1.3 Nomenclature ........................................................................................................ 6 Acronyms............................................................................................................... 6 Conventions........................................................................................................... 6 2.0 Functional Overview ................................................................................................. 8 2.1 2.2 Block Diagram ..................................................................................................... 10 Memory Map........................................................................................................11 3.0 Package Information ............................................................................................... 12 3.1 3.2 56-Lead TSOP Package...................................................................................... 12 Easy BGA Package ............................................................................................. 13 4.0 Ballouts and Signal Descriptions ...................................................................... 15 4.1 4.2 4.3 Easy BGA Ballout (32/64/128 Mbit) ..................................................................... 15 56-Lead TSOP Package Pinout (32/64/128 Mbit) ...............................................16 Signal Descriptions .............................................................................................. 17 5.0 Maximum Ratings and Operating Conditions...............................................19 5.1 5.2 5.3 Absolute Maximum Ratings ................................................................................. 19 Operating Conditions ........................................................................................... 19 Power Up/Down................................................................................................... 20 5.3.1 Power-Up/Down Characteristics............................................................. 20 5.3.2 Power Supply Decoupling.......................................................................20 Reset ................................................................................................................... 20 5.4 6.0 Electrical Characteristics ...................................................................................... 21 6.1 6.2 6.3 DC Current Specifications ................................................................................... 21 DC Voltage specifications.................................................................................... 22 Capacitance......................................................................................................... 23 7.0 AC Characteristics ................................................................................................... 24 7.1 7.2 7.3 7.4 7.5 Read Specifications ............................................................................................. 25 Write Specifications ............................................................................................. 28 Program, Erase, Block-Lock Specifications......................................................... 30 Reset Specifications ............................................................................................31 AC Test Conditions.............................................................................................. 32 8.0 Bus Interface .............................................................................................................. 33 8.1 Bus Reads ........................................................................................................... 34 8.1.1 Asynchronous Page Mode Read ............................................................ 34 8.1.1.1 Enhanced Configuration Register (ECR)................................... 34 8.1.2 Output Disable ........................................................................................ 35 Bus Writes ........................................................................................................... 35 Standby................................................................................................................ 36 8.3.1 Reset/Power-Down ................................................................................. 36 Device Commands .............................................................................................. 36 8.2 8.3 8.4 Datasheet 3 www..com 9.0 Flash Operations ...................................................................................................... 38 9.1 9.2 Status Register .................................................................................................... 38 9.1.1 Clearing the Status Register................................................................... 39 Read Operations ................................................................................................. 39 9.2.1 Read Array ............................................................................................. 39 9.2.2 Read Status Register ............................................................................. 40 9.2.3 Read Device Information ........................................................................ 40 9.2.4 CFI Query ............................................................................................... 41 Programming Operations .................................................................................... 41 9.3.1 Single-Word/Byte Programming ............................................................. 41 9.3.2 Buffered Programming ........................................................................... 42 Block Erase Operations....................................................................................... 43 Suspend and Resume ......................................................................................... 44 Status Signal (STS) ............................................................................................. 45 Security and Protection ....................................................................................... 46 9.7.1 Normal Block Locking............................................................................. 46 9.7.2 Configurable Block Locking .................................................................... 47 9.7.3 OTP Protection Registers....................................................................... 47 9.7.4 Reading the OTP Protection Register .................................................... 48 9.7.5 Programming the OTP Protection Register ............................................ 48 9.7.6 Locking the OTP Protection Register ..................................................... 48 9.7.7 VPP/ VPEN Protection ........................................................................... 50 9.3 9.4 9.5 9.6 9.7 Appendix A Appendix B Appendix C Device Command Codes ................................................................................. 51 J3 v. D ID Codes .................................................................................................. 52 Flow Charts ........................................................................................................... 53 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Write to Buffer...................................................................................................53 Status Register .................................................................................................54 Byte/Word Programming ..................................................................................55 Program Suspend/Resume ..............................................................................56 Block Erase.......................................................................................................57 Block Erase Suspend/Resume .........................................................................58 Block Locking....................................................................................................59 Unlock Block .....................................................................................................60 OTP Protection Register Programming ............................................................61 Appendix D Common Flash Interface ................................................................................. 62 D.2 D.3 D.4 D.5 D.6 D.7 Query Structure Overview ................................................................................63 Block Status Register .......................................................................................64 CFI Query Identification String..........................................................................64 System Interface Information............................................................................65 Device Geometry Definition ..............................................................................66 Primary-Vendor Specific Extended Query Table ..............................................67 Appendix E Appendix F Additional Information...................................................................................... 69 Ordering Information.........................................................................................70 4 Datasheet www..com Revision History Date of Revision July 2005 Version 001 Initial release -Marketing name was changed from 28FxxxJ3 to J3 v. D - Table 18 "Command Bus Operations for J3 v. D" on page 37 was updated September 2005 002 - Section 9.2.2, "Read Status Register" on page 40 - Section 9.3.2, "Buffered Programming" on page 42 - Table 27 "Valid Commands During Suspend" on page 44 - Table 28 "STS Configuration Register" on page 45 was added Description Datasheet 5 www..com 1.0 Introduction This document contains information pertaining to the Intel(R) Embedded Flash Memory (J3 v. D) device features, operation, and specifications. 1.1 Nomenclature AMIN: AMAX: All Densities All Densities 32 Mbit 64 Mbit 128 Mbit Block: Clear: Program: Set: VPEN: V PEN: AMIN = A0 for x8 AMIN = A1 for x16 AMAX = A21 AMAX = A22 AMAX = A23 A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero (0) To write data to the flash array Indicates a logic one (1) Refers to a signal or package connection name Refers to timing or voltage levels 1.2 Acronyms CUI: OTP: PLR: PR: PRD: RFU: SR: SRD: WSM: ECR: Command User Interface One Time Programmable Protection Lock Register Protection Register Protection Register Data Reserved for Future Use Status Register Status Register Data Write State Machine Enhanced Configuration Register 1.3 Conventions h: k (noun): M (noun): Nibble Byte: Hexadecimal Affix 1,000 1,000,000 4 bits 8 bits 6 Datasheet www..com Word: Kword: Kb: KB: Mb: MB: Brackets: 00FFh: 00FF 00FFh: DQ[15:0]: 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]). Denotes 16-bit hexadecimal numbers Denotes 32-bit hexadecimal numbers Data I/O signals 7 Datasheet www..com 2.0 Functional Overview Product Description The Intel(R) Embedded Flash Memory (J3 v. D) family contains high-density memory organized in any of the following configurations: * 16 Mbytes or 8 Mword (128-Mbit), organized as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks * 8 Mbytes or 4 Mword (64-Mbit), organized as sixty-four 128-Kbyte erase blocks * 4 Mbytes or 2 Mword (32-Mbit), organized as thirty-two 128-Kbyte erase blocks These devices can be accessed as 8- or 16-bit words. See Figure 1, "J3 v. D Memory Block Diagram" on page 10 for further details. A 128-bit Protection Register has multiple uses, including unique flash device identification. The Intel(R) Embedded Flash Memory (J3 v. D) device includes new security features that were not available on the (previous) 0.25m and 0.18m versions of the J3 family. These new security features prevent altering of code through different protection schemes that can be implemented, based on user requirements. The J3 v. D device optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 128-Kbyte blocks typically within one second, independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. 8 Datasheet www..com Blocks are selectively and individually lockable in-system. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM's block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design (see Table 15, "Chip Enable Truth Table" on page 33) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device: * BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high byte. * BYTE#-high enables16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care). Figure 1, "J3 v. D Memory Block Diagram" on page 10 shows a device block diagram. When the device is disabled (see Table 15, "Chip Enable Truth Table" on page 33), with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared. 9 Datasheet www..com 2.1 Block Diagram Figure 1. J3 v. D Memory Block Diagram DQ0 - DQ15 VCCQ Output Buffer Input Buffer Output Latch/Multi pl exer Query Write Buffe r Data Register I/O Logic CE Logic VCC BYTE# CE0 CE1 CE2 WE # OE# RP# Identifier Register Status Register Command User Interface A0 - A2 Multiplexer Data Comparator 32-Mbit: A0 - A21 64-Mbit: A0 - A22 128-Mbit: A - A23 0 Y-Decoder Input Buffer Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty -eight Write State Machine Program/Erase Voltage Switch STS V PEN VCC GND Address Latch Address Counter X-Decoder 128-Kbyte Blocks 10 Datasheet www..com 2.2 Memory Map Figure 2. J3 v. D Memory Map A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 0FFFFFF 0FE0000 A [23-1]: 128 Mbit A [22-1]: 64 Mbit A [21-1]: 32 Mbit 7FFFFF 127 7F0000 128-Kbyte Block 64-Kword Block 127 07FFFFF 07E0000 128-Kbyte Block 3FFFFF 63 3F0000 64-Kword Block 63 128-Kbyte Block 31 1F0000 64-Kword Block 31 03E0000 003FFFF 0020000 001FFFF 0000000 128-Kbyte Block 128-Kbyte Block 01FFFF 1 010000 00FFFF 0 000000 64-Kword Block 64-Kword Block 1 0 Byte-Wide (x8) Mode Word Wide (x16) Mode 32-Mbit 64-Mbit 03FFFFF 1FFFFF 128-Mbit 11 Datasheet www..com 3.0 3.1 Package Information 56-Lead TSOP Package Figure 3. 56-Lead TSOP Package Mechanical Z See Notes 1 and 3 Pin 1 See Note 2 A2 e E See Detail B Y D1 D A1 Seating Plane See Detail A A Detail A Detail B C 0 b L Table 1. 56-Lead TSOP Dimension Table (Sheet 1 of 2) Millimeters Sym Min Nom Max 1.200 0.050 0.965 0.100 0.100 18.200 13.800 0.995 0.150 0.150 18.400 14.000 0.500 19.800 0.500 20.00 0.600 56 20.200 0.700 0.780 0.020 1.025 0.200 0.200 18.600 14.200 0.002 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 0.787 0.024 56 0.795 0.028 0.040 0.008 0.008 0.732 0.559 Min Inches Nom Max 0.047 Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count A A1 A2 b c D1 E e D L N 12 Datasheet www..com Table 1. 56-Lead TSOP Dimension Table (Sheet 2 of 2) Millimeters Sym Min 0 Nom 3 Max 5 0.100 0.150 0.250 0.350 0.006 0.010 Min 0 Inches Nom 3 Max 5 0.004 0.014 Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset Y Z 3.2 Easy BGA Package Figure 4. Easy BGA Mechanical Specifications Ball A1 Corner Ball A1 Corner S1 D 1 A B C D E E F G H 2 3 4 5 6 7 8 A B C D E F G 8 7 6 5 4 3 2 1 S2 b e H Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Plane Y Note: Drawing not to scale 13 Datasheet www..com Table 2. Easy BGA Package Dimensions Table Millimeters Symbol Min Nom Max 1.200 0.250 0.780 0.330 9.900 12.900 0.430 10.000 13.000 1.000 64 0.100 1.400 2.900 1.500 3.000 1.600 3.100 1 1 0.0551 0.1142 0.0591 0.1181 0.530 10.100 13.100 1 1 0.0130 0.3898 0.5079 0.0098 0.0307 0.0169 0.3937 0.5118 0.0394 64 0.0039 0.0630 0.1220 0.0209 0.3976 0.5157 Notes Min Inches Nom Max 0.0472 Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width (32 Mb, 64 Mb, 128 Mb) Package Body Length (32 Mb, 64 Mb, 128 Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32/64/128 Mb) Corner to Ball A1 Distance Along E (32/64/128 Mb) A A1 A2 b D E [e] N Y S1 S2 NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at: www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at: www.intel.com/ design/packtech/index.htm 14 Datasheet www..com 4.0 Ballouts and Signal Descriptions Intel(R) Embedded Flash Memory (J3 v. D) is available in two package types. Each density of the J3 v. D is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. Figure 5, and Figure 6 show the pinouts. 4.1 Easy BGA Ballout (32/64/128 Mbit) Figure 5. Easy BGA Ballout (32/64/128 Mbit) 1 A A1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1 B A2 VSS A9 CE0# A14 RFU A19 CE1# CE1# A19 RFU A14 CE0# A9 VSS A2 B C A3 A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3 C D A4 A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4 D E D8 D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8 E F BYTE# D0 D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE# F G A23 A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23 G H CE2# RFU VCC VSS D13 VSS D7 RFU RFU D7 VSS D13 VSS VCC RFU CE2# Intel(R) Embedded Flash Memory (28FXXXJ3D) Easy BGA Top View- Ball side down 32/64/128 Mbit Intel(R) Embedded Flash Memory (28FXXXJ3D) Easy BGA Bottom View- Ball side up 32/64/128 Mbit H NOTES: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC). 15 Datasheet www..com 4.2 56-Lead TSOP Package Pinout (32/64/128 Mbit) Figure 6. 56-Lead TSOP Package Pinout (32/64/128 Mbit) RFU WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# A23 CE2 A22 CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Intel(R) Embedded Flash Memory (28FXXXJ3D) 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View 32/64/128 Mbit 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NOTES: 1. A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC) 16 Datasheet www..com 4.3 Signal Descriptions Table 3 lists the active signals used on J3 v. D and provides a description of each. Table 3. Symbol Signal Descriptions for J3 v. D (Sheet 1 of 2) Type Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle: A0 Input A[MAX:1] Input 32-Mbit -- A[21:1] 64-Mbit -- A[22:1] 128-Mbit -- A[23:1] LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data is internally latched during write operations. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode CHIP ENABLES: Activate the 32-, 64- and 128 Mbit devices' control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 15, "Chip Enable Truth Table" on page 33), power reduces to standby levels. D[7:0] Input/Output D[15:8] Input/Output CE[2:0] Input All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0#, CE1#, or CE2# that enables the device. Device deselection occurs with the first edge of CE0#, CE1#, or CE2# that disables the device (see Table 15, "Chip Enable Truth Table" on page 33). RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of WE#. STATUS: Indicates the status of the internal state machine. When configured in level mode (default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS signal, see the Configurations command and Section 9.6, "Status Signal (STS)" on page 45. STS is to be tied to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order address bit. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. RP# Input OE# WE# Input Input STS Open Drain Output BYTE# Input VPEN Input With VPEN VPENLK, memory contents cannot be altered. VCC VCCQ Power Power CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC VLKO. Caution: Device operation at invalid Vcc voltages should not be attempted. I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC. 17 Datasheet www..com Table 3. Symbol Signal Descriptions for J3 v. D (Sheet 2 of 2) Type Name and Function Ground: Ground reference for device logic voltages. Connect to system ground. No Connect: Lead is not internally connected; it may be driven or floated. Reserved for Future Use: Balls designated as RFU are reserved by Intel for future device functionality and enhancement. GND NC RFU Supply -- -- 18 Datasheet www..com 5.0 5.1 Warning: Maximum Ratings and Operating Conditions Absolute Maximum Ratings Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Table 4. Absolute Maximum Ratings Parameter Min Max Unit Notes Temperature under Bias Expanded (TA, Ambient) Storage Temperature VCC Voltage VCCQ Voltage on any input/output signal (except VCC, VCCQ) ISH Output Short Circuit Current -40 -65 -2.0 -2.0 -2.0 -- +85 +125 +5.6 +5.6 VCCQ (max) + 2.0 100 C C V V V mA -- -- 2 2 1 3 NOTES: 1. Voltage is referenced to VSS. During infrequent non-periodic transitions, the voltage potential between VSS and input/output pins may undershoot to -2.0 V for periods < 20 ns or overshoot to VCCQ (max) + 2.0 V for periods < 20 ns. 2. During infrequent non-periodic transitions, the voltage potential between VCC and the supplies may undershoot to - 2.0 V for periods < 20 ns or VSUPPLY (max) + 2.0 V for periods < 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time 5.2 Warning: Operating Conditions Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Table 6. Temperature and VCC Operating Condition of J3 v. D Parameter Min Max Unit Test Condition Symbol TA VCC VCCQ VCC Supply Voltage VCCQ Supply Voltage -40.0 2.70 2.70 +85 3.6 3.6 C V V Ambient Temperature -- -- 19 Datasheet www..com 5.3 Power Up/Down This section provides an overview of system level considerations with regards to the flash device. It includes a brief description of power-up, power-down and decoupling design considerations. 5.3.1 Power-Up/Down Characteristics To prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up and power-down VCC and VCCQ together. It is also recommended to: * Power-up VPEN after VCC=VCCmin * Power-down VPEN with or before VCC 5.3.2 Power Supply Decoupling When the device is enabled, many internal conditions change. Circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. All of this internal activities produce transient signals. The magnitude of the transient signals depends on the device and system loading. To minimize the effect of these transient signals, a 0.1 F ceramic capacitor is required across each VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device connections. Additionally, for every eight flash devices, a 4.7 F electrolytic capacitor should be placed between VCC and VSS at the power supply connection. This 4.7 F capacitor should help overcome voltage slumps caused by PCB (printed circuit board) trace inductance. 5.4 Reset By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 12, "AC Waveform for Reset Operation" on page 31 for detailed information regarding reset timings. 20 Datasheet www..com 6.0 6.1 Table 7. Electrical Characteristics DC Current Specifications DC Current Characteristics (Sheet 1 of 2) VCCQ VCC 2.7 - 3.6V 2.7 - 3.6V Typ Max 1 10 Unit A A Test Conditions Notes Symbol Parameter ILI ILO Input and VPEN Load Current Output Leakage Current VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or VSS VCC= VCC Max; VCCQ = VCCQ Max VIN = VCCQ or VSS CMOS Inputs, VCC = VCC Max; Vccq = VccqMax Device is disabled (see Table 15, "Chip Enable Truth Table" on page 33), RP# = VCCQ 0.2 V TTL Inputs, VCC = VCC Max, Vccq = VccqMax Device is disabled (see Table 15, "Chip Enable Truth Table" on page 33), RP# = VIH RP# = GND 0.2 V, IOUT (STS) = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max 1 1 50 ICCS VCC Standby Current 0.71 120 A 1,2,3 2 mA A ICCD VCC Power-Down Current 50 120 15 4Word Page 24 20 mA Device is enabled (see Table 15, "Chip Enable Truth Table" on page 33) f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max 29 mA Device is enabled (see Table 15, "Chip Enable Truth Table" on page 33) f = 33 MHz, IOUT = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. Device is enabled (see Table 15, "Chip Enable Truth Table" on page 33) f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. 1,3 ICCR VCC Page Mode Read Current 10 15 mA 8Word Page 30 54 mA Device is enabled (see Table 15, "Chip Enable Truth Table" on page 33) f = 33 MHz, IOUT = 0 mA Density: 128-, 64-, and 32- Mbit CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC ICCW VCC Program or Set Lock-Bit Current 35 40 60 70 mA mA 1,4 21 Datasheet www..com Table 7. DC Current Characteristics (Sheet 2 of 2) VCCQ VCC 2.7 - 3.6V 2.7 - 3.6V Typ Max Unit Test Conditions Notes Symbol Parameter ICCE ICCWS ICCES VCC Block Erase or Clear Block Lock-Bits Current VCC Program Suspend or Block Erase Suspend Current 35 40 70 80 10 mA mA mA CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC Device is enabled (see Table 15, "Chip Enable Truth Table" on page 33) 1,4 1,5 NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel's Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH. 4. Sampled, not 100% tested. 5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the device's current draw is ICCR and ICCWS. 6.2 Table 8. DC Voltage specifications DC Voltage Characteristics (Sheet 1 of 2) VCCQ VCC 2.7 - 3.6 V 2.7 - 3.6 V Min Max Unit Test Conditions Notes Symbol Parameter VIL VIH Input Low Voltage Input High Voltage -0.5 2.0 0.8 VCCQ + 0.5V 0.4 V V VCC = VCCMin V VCCQ = VCCQ Min IOL = 2 mA VCC = VCCMin VCCQ = VCCQ Min IOL = 100 A VCC = VCCMIN V VCCQ = VCCQ Min IOH = -2.5 mA VCC = VCCMIN VCCQ = VCCQ Min IOH = -100 A 2, 6, 7 2, 6, 7 VOL Output Low Voltage 0.2 V 1, 2 0.85 x VCCQ VOH Output High Voltage VCCQ - 0.2 VPEN Lockout during Program, Erase and Lock-Bit Operations 1, 2 V VPENLK 2.2 V 2, 3, 4 22 Datasheet www..com Table 8. DC Voltage Characteristics (Sheet 2 of 2) VCCQ VCC 2.7 - 3.6 V 2.7 - 3.6 V Min Max Unit Test Conditions Notes Symbol Parameter VPENH VLKO VPEN during Block Erase, Program, or Lock-Bit Operations VCC Lockout Voltage 2.7 2.0 3.6 V V 3, 4 5 NOTES: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 4. Typically, VPEN is connected to VCC (2.7 V-3.6 V). 5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). 6. Includes all operational modes of the device including standby and power-up sequences 7. Input/Output signals can undershoot to -1.0v referenced to VSS and can overshoot to VCCQ = 1.0v for duration of 2ns or less, the VCCQ valid range is referenced to VSS. 6.3 Capacitance Table 9. Symbol J3 v. D Capacitance Parameter1 Type Max Unit Condition2 CIN COUT Input Capacitance Output Capacitance 6 8 8 12 pF pF VIN = 0.0 V VOUT = 0.0 V NOTES: 1. sampled. not 100% tested. 2. TA = +25 C, f = 1 MHZ 23 Datasheet www..com 7.0 AC Characteristics Timing symbols used in the timing diagrams within this document conform to the following convention: t Source Signal Source State Signal ELQV Target State Target Signal Code State Code Address Data - Read Data - Write Chip Enable (CE#) Output Enable (OE#) Write Enable (WE#) Address Valid (ADV#) Reset (RST#) Clock (CLK) WAIT A Q D E G W V P C T High Low High-Z Low-Z Valid Invalid H L Z X V I Note: Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash device's data sheet, and is the address-to-data delay for subsequent page-mode reads. 24 Datasheet www..com 7.1 Read Specifications Table 10. Read Operations Asynchronous Specifications VCC = 2.7 V-3.6 V (3) VCCQ = 2.7 V-3.6 V(3) -75 # Sym Parameter Density Min Max Min Max -95 Unit Notes 32 Mbit R1 tAVAV Read/Write Cycle Time 64 Mbit 128 Mbit 32 Mbit R2 tAVQV Address to Output Delay 64 Mbit 128 Mbit 32 Mbit R3 tELQV CEX to Output Delay 64 Mbit 128 Mbit R4 tGLQV OE# to Non-Array Output Delay 32 Mbit R5 tPHQV RP# High to Output Delay 64 Mbit 128 Mbit R6 R7 R8 R9 R10 tELQX tGLQX tEHQZ tGHQZ tOH tELFL/ tELFH tFLQV/ tFHQV tFLQZ tEHEL tAPA CEX to Output in Low Z OE# to Output in Low Z CEX High to Output in High Z OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low BYTE# to Output Delay BYTE# to Output in High Z CEx High to CEx Low All R15 Page Address Access Time All 75 75 75 75 75 75 75 75 75 25 150 180 210 0 0 25 15 0 0 0 0 25 15 ns ns ns ns ns ns 25 ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,4 1,2 1,2 1,2 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 R11 R12 R13 R14 10 1 1 0 25 0 10 1 1 ns s s ns 1,2,5 1,2 1,2,5 1,2,5 5, 6 25 ns NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, "Chip Enable Truth Table" on page 33). 1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 15, "Chip Enable Truth Table" on page 33) without impact on tELQV. 25 Datasheet www..com 3. See Figure 13, "AC Input/Output Reference Waveform" on page 32 and Figure 14, "Transient Equivalent Testing Load Circuit" on page 32 for testing characteristics. 4. Sampled, not 100% tested. 5. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV). Figure 7. Single Word Asynchronous Read Waveform R1 R2 Address [A] R3 CEx [E] R9 OE# [G] WE# [W] R4 R16 R7 R6 Data [D/Q] R11 BYT E#[F] R5 RP# [P] R12 R13 R10 R8 NOTES: 1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, "Chip Enable Truth Table" on page 33). 2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads, query reads, or device identifier reads). 26 Datasheet www..com Figure 8. 4-Word Asynchronous Page Mode Read Waveform R1 R2 A[MAX:3] [A] A[2:1] [A] R3 CEx [E] R4 OE# [G] WE# [W] R8 R10 R9 2 3 4 00 01 10 11 R6 R7 D[15:0] [Q] R5 RP# [P] 1 R10 R15 NOTE: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, "Chip Enable Truth Table" on page 33). Figure 9. 8-Word Asynchronous Page Mode Read R1 R2 A[MAX:4] [A] A[3:1] [A] R3 CEx [E] R4 OE# [G] WE# [W] R10 R8 R9 7 8 R6 R7 D[15:0] [Q] R5 RP# [P] BYTE# 1 R10 R15 2 NOTES: 1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, "Chip Enable Truth Table" on page 33). 2. In this diagram, BYTE# is asserted high 27 Datasheet www..com 7.2 Write Specifications Table 11. Write Operations Valid for All Speeds Min Max # Symbol Parameter Density Unit Notes 32 Mbit W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX) Going Low 64 Mbit 128 Mbit W2 W3 W4 W5 W6 W7 W8 W9 W11 W12 W13 W15 NOTES: 150 180 210 0 60 50 55 0 0 ns 1,2,3 tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CEX) Going High Address Setup to WE# (CEX) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High Write Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to STS Going Low VPEN Hold from Valid SRD, STS Going High All 1,2,4 1,2,4 1,2,5 1,2,5 1,2, 1,2, 1,2, 1,2,6 1,2,3 1,2,7 500 1,2,8 1,2,3,8,9 0 30 0 35 0 CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, "Chip Enable Truth Table" on page 33). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics-Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . 5. Refer to Table 16, "Enhanced Configuration Register" on page 35 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[1,3,4,5] = 0). 28 Datasheet www..com Figure 10. Asynchronous Write Waveform W5 ADDRESS [A] W6 CEx (WE#) [E (W)] W2 WE# (CEx) [W (E)] OE# [G] W4 DATA [D/Q] D W13 ST S[R] W1 RP# [P] W11 VPEN [V] W7 W3 W9 W8 Figure 11. Asynchronous Write to Read Waveform W5 Address [A] W6 CE# [E] W2 WE# [W] W12 OE# [G] W4 Data [D/Q] W1 RST#/ RP# [P] W11 VPEN [V] D W7 W3 W8 _ 29 Datasheet www..com 7.3 Program, Erase, Block-Lock Specifications Table 12. Configuration Performance # Symbol Parameter Typ Max(8) Unit Notes W16 W16 tWHQV3 tEHQV3 Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command) 128 40 0.53 1.0 50 0.5 15 15 500 475 654 175 2.4 4.0 60 0.70 20 20 s s sec sec s sec s s ns s 1,2,3,4,5,6,7 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4,9 1,2,3,4,9 1,2,3,9 1,2,3,9 1 1, 10 W16 W16 W16 W16 W16 WY WX tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH tSTS tWHWH Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read STS Pulse Width Low Time Resume Latency to Program/Erase NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. These performance numbers are valid for all speed versions. 3. Sampled but not 100% tested. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (tWHQV1, tEHQV1) is 4s/byte (typical). 7. Effective per-word program time (tWHQV2, tEHQV2) is 8s/word (typical). 8. Max values are measured at worst case temperature, data pattern and VCC corner after 100k cycles (except as noted). 9. Max values are expressed at 25 C/-40 C. 10.WX is the minimum time from Erase Resume to an Erase Suspend state. Repeatedly suspending the device more often may have undetermined effects. 30 Datasheet www..com 7.4 Reset Specifications Figure 12. AC Waveform for Reset Operation STS (R) P1 RP# (P) P3 Vcc NOTE: STS is shown in its default mode (RY/BY#) P2 Table 13. Reset Specifications # Symbol Parameter Min Max Unit Notes P1 tPLPH tPHRH tVCCPH RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration Vcc Power Valid to RP# de-assertion (high) 25 s 1,2 P2 P3 100 60 ns s 1,3 NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid. 31 Datasheet www..com 7.5 AC Test Conditions Figure 13. AC Input/Output Reference Waveform VCCQ Input VCCQ/2 0.0 NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns. Test Points VCCQ/2 Output Figure 14. Transient Equivalent Testing Load Circuit Device Under Test CL Out NOTE: CL Includes Jig Capacitance Test Configuration CL (pF) VCCQ = VCCQMIN 30 32 Datasheet www..com 8.0 Bus Interface This section provides an overview of Bus operations. Basically, there are three operations you can do with flash memory: Read, Program (Write), and Erase.The on-chip Write State Machine (WSM) manages all erase and program algorithms. The system CPU provides control of all in-system read, write, and erase operations through the system bus. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 14 summarizes the necessary states of each control signal for different modes of operations. Table 14. Bus Operations Mode RP# CEx(1) OE#(2) WE#(2) VPEN DQ15:0(3) STS (Default Mode) Notes Async., Status, Query and Identifier Reads Output Disable Standby Reset/Power-down Command Writes Array Writes (8) VIH VIH VIH VIL VIH VIH Enabled Enabled Disabled X Enabled Enabled VIL VIH X X VIH VIH VIH VIH X X VIL VIL X X X X X VPENH DOUT High Z High Z High Z DIN X High Z High Z High Z High Z High Z VIL 4,6 6,7 8,5 NOTES: 1. See Table 15 for valid CEx Configurations. 2. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#. 3. DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high. 4. Refer to DC characteristics. When VPEN VPENLK, memory contents can be read but not altered. 5. X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration algorithm. It is VOH (pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset powerdown mode. 7. See Table 18, "Command Bus Operations for J3 v. D" on page 37 for valid DIN (user commands) during a Write operation 8. Array writes are either program or erase operations. / Table 15. Chip Enable Truth Table CE2 CE1 CE0 DEVICE VIL VIL VIL VIL VIH VIH VIH VIH VIL VIL VIH VIH VIL VIL VIH VIH VIL VIH VIL VIH VIL VIH VIL VIH Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled NOTE: For single-chip applications, CE2 and CE1 can be connected to GND. The next few sections detail each of the basic flash operations and some of the advanced features available on flash memory. 33 Datasheet www..com 8.1 Bus Reads Reading from flash memory outputs stored information to the processor or chipset, and does not change any contents. Reading can be performed an unlimited number of times. Besides array data, other types of data such as device information and device status is available from the flash. To perform a bus read operation, CEx (refer to Table 15 on page 33) and OE# must be asserted. CEx is the device-select control; when active, it enables the flash memory device. OE# is the dataoutput control; when active, the addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See Section 9.2, "Read Operations" on page 39. 8.1.1 Asynchronous Page Mode Read There are two Asynchronous Page mode configurations available on J3 v. D, depending on the system design requirements: * Four-Word Page mode: This is the default mode on power-up or reset. Array data can be sensed up to four words (8 Bytes) at a time. * Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This mode must be enabled on power-up or reset by using the command sequence described in Table 18 on page 37. Address bits A[3:1] determine which word is output during a read operation, and A[3:0] determine which byte is output for a x8 bus width. After the initial access delay, the first word out of the page buffer corresponds to the initial address. In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus width. Subsequent reads from the device come from the page buffer. These reads are output on D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0] (Four-Word Page mode) or A[3:0] (Eight-Word Page mode). Data can be read from the page buffer multiple times, and in any order. In Four-Word Page mode, if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is toggled, the device will sense and load new data into the page buffer. Asynchronous Page mode is the default read mode on power-up or reset. To perform a Page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous Page mode reads are permitted in all blocks and are used to access register information. During register access, only one word is loaded into the page buffer. 8.1.1.1 Enhanced Configuration Register (ECR) The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed by the Set Enhanced Configuration Register command can select between Four-Word Page mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set Enhanced Configuration Register command. The Set Enhanced Configuration Register command is written along with the configuration register value, which is placed on the lower 16 bits of the address bus A[15:0]. This is followed by a second write that confirms the operation and again presents the Enhanced Configuration Register data on the address bus. After executing this command, the device returns to Read Array mode. The ECR is shown in Table 16. 8-word page mode Command Bus-Cycle is captured in Table 17. 34 Datasheet www..com Note: For forward compatibility reasons, if the 8-word Asynchronous Page mode is used on J3 v. D, a Clear Status Register command must be executed after issuing the Set Enhanced Configuration Register command. See Table 17 for further details. Table 16. Enhanced Configuration Register Reserved Page Length Reserved ECR 15 ECR 14 ECR 13 ECR 12 ECR 11 ECR 10 ECR 9 ECR 8 ECR 7 ECR 6 ECR 5 ECR 4 ECR 3 ECR 2 ECR 1 ECR 0 BITS DESCRIPTION NOTES ECR[15:14] ECR[13] ECR[12:0] RFU * "1" = 8 Word Page mode * "0" = 4 Word Page mode RFU All bits should be set to 0. All bits should be set to 0. Table 17. J3 v. D Asynchronous 8-Word Page Mode Command Bus-Cycle Definition Command Bus Cycles Required First Bus Cycle Oper Addr(1) Data Oper Second Bus Cycle Addr(1) Data Set Enhanced Configuration Register (Set ECR) 2 Write ECD 0060h Write ECD 0004h 1. X = Any valid address within the device. ECD = Enhanced Configuration Register Data 8.1.2 Output Disable With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output signals D[15:0] are placed in a high-impedance state. 8.2 Bus Writes Writing or Programming to the device, is where the host writes information or data into the flash device for non-volatile storage. When the flash device is programmed, `ones' are changed to `zeros'. `Zeros' cannot be programed back to `ones'. To do so, an erase operation must be performed. Writing commands to the Command User Interface (CUI) enables various modes of operation, including the following: * * * * Reading of array data Common Flash Interface (CFI) data Identifier codes, inspection, and clearing of the Status Register Block Erasure, Program, and Lock-bit Configuration (when VPEN = V PENH) Erasing is performed on a block basis - all flash cells within a block are erased together. Any information or data previously stored in the block will be lost. Erasing is typically done prior to programming. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and 35 Datasheet www..com address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device to be cleared. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 15 on page 33). Standard microprocessor write timings are used. 8.3 Standby CE0, CE1, and CE2 can disable the device (see Table 15 on page 33) and place it in standby mode. This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes. 8.3.1 Reset/Power-Down RP# at V IL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and Status Register is set to 0080h. During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (V IH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during Block Erase, Program, or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel(R) Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 8.4 Device Commands When the VPEN voltage V PENLK, only read operations from the Status Register, CFI, identifier codes, or blocks are enabled. Placing V PENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands to the Command User Interface (CUI). The CUI does not occupy an addressable memory location. It is the mechanism through which the flash device is controlled. 36 Datasheet www..com A command sequence is issued in two consecutive write cycles - a Setup command followed by a Confirm command. However, some commands are single-cycle commands consisting of a setup command only. Generally, commands that alter the contents of the flash device, such as Program or Erase, require at least two write cycles to guard against inadvertent changes to the flash device. Flash commands fall into two categories: Basic Commands and Extended Commands. Basic commands are recognized by all Intel(R) Flash devices, and are used to perform common flash operations such as selecting the read mode, programming the array, or erasing blocks. Extended commands are product-dependant; they are used to perform additional features such as software block locking. Table 18 describes all applicable commands on Intel(R) Embedded Flash Memory (J3 v. D). Table 18. Command Bus Operations for J3 v. D Setup Write Cycle Command Address Bus Data Bus Address Bus Data Bus Confirm Write Cycle Program Enhanced Configuration Register Registers Register Data Device Address Device Address Device Address Device Address Device Address Device Address Device Address Device Address Word Address Device Address Device Address Device Address Block Address Block Address 0060h 00C0h 0050h 00BS8h 00FFh 0070h 0090h 0098h 0040h/ 0010h 00E8h 0020h 00B0h 00D0h 0060h 0060h Register Data Register Offset --Device Address --------Device Address Device Address Block Address ----Block Address Block Address 0004h Register Data --Register Data --------Array Data 00D0h 00D0h ----0001h 00D0h Program OTP Register Clear Status Register Program STS Configuration Register Read Modes Program and Erase Security Read Array Read Status Register Read Identifier Codes (Read Device Information) CFI Query Word/Byte Program Buffered Program Block Erase Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block 37 Datasheet www..com 9.0 Flash Operations This section describes the operational features of flash memory. Operations are command-based, wherein command codes are first issued to the device, then the device performs the desired operation. All command codes are issued to the device using bus-write cycles (see Chapter 8.0, "Bus Interface"). A complete list of available command codes can be found in Appendix A, "Device Command Codes". 9.1 Status Register The Status Register (SR) is an 8-bit, read-only register that indicates device status and operation errors. To read the Status Register, issue the Read Status Register command. Subsequent reads output Status Register information on DQ[7:0], and 00h on DQ[15:8]. SR status bits are set and cleared by the device. SR error bits are set by the device, but must be cleared using the Clear Status Register command. Upon power-up or exit from reset, the Status Register defaults to 80h. Page-mode reads are not supported in this read mode. Status Register contents are latched on the falling edge of OE# or the first edge of CEx that enables the device. OE# must toggle to VIH or the device must be disabled before further reads to update the Status Register latch. The Read Status Register command functions independently of VPEN voltage. Table 19 shows Status Register bit definitions. Table 19. Status Register Bit Definitions Status Register (SR) Ready Status Erase Suspend Status 6 Name Erase Error Program Error Program /Erase Voltage Error 3 Program Suspend Status 2 Description Default Value = 80h BlockLocked Error 1 Reserved 7 Bit 5 4 0 7 6 Ready Status Erase Suspend Status 0 = Device is busy; SR[6:0] are invalid (Not driven); 1 = Device is ready; SR[6:0] are valid. 0 = Erase suspend not in effect. 1 = Erase suspend in effect. SR5 SR4 0 0 = Program or erase operation successful. 0 1 = Program error - operation aborted. 1 0 = Erase error - operation aborted. 1 1 = Command sequence error - command aborted. 0 = VPEN within acceptable limits during program or erase operation. 1 = VPEN not within acceptable limits during program or erase operation. Operation aborted. 0 = Program suspend not in effect. 1 = Program suspend in effect. 0 = Block NOT locked during program or erase - operation successful. 1 = Block locked during program or erase - operation aborted. Not used - Reserved for future use. 5 Erase Error Program Error VPEN Error Command Sequence Error 4 3 2 1 0 Program Suspend Status Block-Locked Error Reserved 38 Datasheet www..com 9.1.1 Clearing the Status Register The Status Register (SR) contain status and error bits which are set by the device. SR status bits are cleared by the device, however SR error bits are cleared by issuing the Clear Status Register command (see Table 20). Resetting the device also clears the Status Register. Table 20. Clear Status Register Command Bus-Cycle Command Setup Write Cycle Address Bus Data Bus Confirm Write Cycle Address Bus Data Bus Clear Status Register Device Address 0050h --- --- Issuing the Clear Status Register command places the device in Read Status Register mode. Note: Care should be taken to avoid Status Register ambiguity. If a command sequence error occurs while in an Erase Suspend condition, the Status Register will indicate a Command Sequence error by setting SR4 and SR5. When the erase operation is resumed (and finishes), any errors that may have occurred during the erase operation will be masked by the Command Sequence error. To avoid this situation, clear the Status Register prior to resuming a suspended erase operation. The Clear Status Register command functions independent of the voltage level on VPEN. 9.2 Read Operations Four types of data can be read from the device: array data, device information, CFI data, and device status. Upon power-up or return from reset, the device defaults to Read Array mode. To change the device's read mode, the appropriate command must be issued to the device. Table 21 shows the command codes used to configure the device for the desired read mode. The following sections describe each read mode. Table 21. Read Mode Command Bus-Cycles Command Setup Write Cycle Address Bus Data Bus Confirm Write Cycle Address Bus Data Bus Read Array Read Status Register Read Device Information CFI Query Device Address Device Address Device Address Device Address 00FFh 0070h 0090h 0098h --------- --------- 9.2.1 Read Array Upon power-up or return from reset, the device defaults to Read Array mode. Issuing the Read Array command places the device in Read Array mode. Subsequent reads output array data on DQ[15:0]. The device remains in Read Array mode until a different read command is issued, or a program or erase operation is performed, in which case, the read mode is automatically changed to Read Status. 39 Datasheet www..com To change the device to Read Array mode while it is programming or erasing, first issue the Suspend command. After the operation has been suspended, issue the Read Array command. When the program or erase operation is subsequently resumed, the device will automatically revert back to Read Status mode. Note: Issuing the Read Array command to the device while it is actively programming or erasing causes subsequent reads from the device to output invalid data. Valid array data is output only after the program or erase operation has finished. The Read Array command functions independent of the voltage level on VPEN. 9.2.2 Read Status Register Issuing the Read Status Register command places the device in Read Status Register mode. Subsequent reads output Status Register information on DQ[7:0], and 00h on DQ[15:8]. The device remains in Read Status Register mode until a different read-mode command is issued. Performing a program, erase, or block-lock operation also changes the device's read mode to Read Status Register mode. The Status Register is updated on the falling edge of CE#, or OE# when CE# is low. Status Register contents are valid only when SR7 = 1. When WSM us active, SR7 indicates the WSM's state and SR[6:0] are in hig-Z state. The Read Status Register command functions independent of the voltage level on VPEN. 9.2.3 Read Device Information Issuing the Read Device Information command places the device in Read Device Information mode. Subsequent reads output device information on DQ[15:0] (see Table 22). Table 22. Device Information Summary Device Information Word Address DQ[15:0] Device Manufacturer Code (Intel) Device ID Code Block Lock Status OTP Lock Register OTP Register - Factory Segment OTP Register - User-Programmable Segment Device Base Address + 00h Device Base Address + 01h Block Base Address + 02h Device Base Address + 80h Device Base Address + 81h to 84h Device Base Address + 85h to 88h 0089h (See Appendix B, "J3 v. D ID Codes") DQ0 = 0 Unlocked DQ0 = 1 Locked DQ[15:1] = RFU Lock Register 0 Data Factory-Programmed Data User Data The device remains in Read Device Information mode until a different read command is issued. Also, performing a program, erase, or block-lock operation changes the device to Read Status Register mode. The Read Device Information command functions independent of the voltage level on VPEN. 40 Datasheet www..com 9.2.4 CFI Query The query table contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications, and other product information. The data contained in this table conforms to the Common Flash Interface (CFI) protocol. Issuing the CFI Query command places the device in CFI Query mode. Subsequent reads output CFI information on DQ[15:0] (see Appendix D, "Common Flash Interface"). The device remains in CFI Query mode until a different read command is issued, or a program or erase operation is performed, which changes the read mode to Read Status Register mode. The CFI Query command functions independent of the voltage level on VPEN. 9.3 Programming Operations Programming the flash array changes `ones' to `zeros'. To change zeros to ones, an erase operation must be performed (see Section 9.4, "Block Erase Operations"). Only one programming operation can occur at a time. Programming is permitted during an erase suspend. Information is programmed into the flash array by issuing the appropriate command. J3 v. D supports two different programming methods: Byte/Word and Write-to-Buffer. Table 24 shows the two-cycle command sequences used for each method. Table 24. Program Command Bus-Cycles Command Setup Write Cycle Address Bus Data Bus Confirm Write Cycle Address Bus Data Bus Single-Word/Byte Program Buffered Program Device Address Device Address 0040h/0010h 00E8h Device Address Device Address Array Data 00D0h Note: All programming operations require the addressed block to be unlocked, and a valid VPEN voltage applied throughout the programming operation. Otherwise, the programming operation will abort, setting the appropriate Status Register error bit(s). The following sections describe each programming method. 9.3.1 Single-Word/Byte Programming Array programming is performed by first issuing the Single-Word/Byte Program command. This is followed by writing the desired data at the desired array address. The read mode of the device is automatically changed to Read Status Register mode, which remains in effect until another readmode command is issued. During programming, STS and the Status Register indicate a busy status (SR7 = 0). Upon completion, STS and the Status Register indicate a ready status (SR7 = 1). The Status Register should be checked for any errors (SR4), then cleared. 41 Datasheet www..com Note: Issuing the Read Array command to the device while it is actively programming causes subsequent reads from the device to output invalid data. Valid array data is output only after the program operation has finished. Standby power levels are not be realized until the programming operation has finished. Also, asserting RP# aborts the programming operation, and array contents at the addressed location are indeterminate. The addressed block should be erased, and the data re-programmed. If a SingleWord/Byte program is attempted when the corresponding block lock-bit is set, SR1 and SR4 will be set. 9.3.2 Buffered Programming Buffered programming operations simultaneous program multiple words into the flash memory array, significantly reducing effective word-write times. User-data is first written to a write buffer, then programmed into the flash memory array in buffer-size increments. Appendix C, "Flow Charts" contains a flow chart of the buffered-programming operation. Note: Optimal performance and power consumption is realized only by aligning the start address on 32word boundaries (i.e., A[4:0] = 0b00000). Crossing a 32-word boundary during a buffered programming operation can cause programming time to double. To perform a buffered programming operation, first issue the Buffered Program setup command at the desired starting address. The read mode of the device/addressed partition is automatically changed to Read Status Register mode. Polling SR7 determines write-buffer availability (0 = not available, 1 = available). If the write buffer is not available, re-issue the setup command and check SR7; repeat until SR7 = 1. Next, issue the word count at the desired starting address. The word count represents the total number of words to be written into the write buffer, minus one. This value can range from 00h (one word) to a maximum of 1Fh (32 words). Exceeding the allowable range causes an abort. Following the word count, the write buffer is filled with user-data. Subsequent bus-write cycles provide addresses and data, up to the word count. All user-data addresses must lie between 42 Datasheet www..com Additional buffered programming operations can be initiated by issuing another setup command, and repeating the buffered programming bus-cycle sequence. However, any errors in the Status Register must first be cleared before another buffered programming operation can be initiated. 9.4 Block Erase Operations Erasing a block changes `zeros' to `ones'. To change ones to zeros, a program operation must be performed (see Section 9.3, "Programming Operations"). Erasing is performed on a block basis an entire block is erased each time an erase command sequence is issued. Once a block is fully erased, all addressable locations within that block read as logical ones (FFFFh). Only one blockerase operation can occur at a time, and is not permitted during a program suspend. To perform a block-erase operation, issue the Block Erase command sequence at the desired block address. Table 25 shows the two-cycle Block Erase command sequence. Table 25. Block-Erase Command Bus-Cycle Command Setup Write Cycle Address Bus Data Bus Confirm Write Cycle Address Bus Data Bus Block Erase Device Address 0020h Block Address 00D0h Note: A block-erase operation requires the addressed block to be unlocked, and a valid voltage applied to VPEN throughout the block-erase operation. Otherwise, the operation will abort, setting the appropriate Status Register error bit(s). The Erase Confirm command latches the address of the block to be erased. The addressed block is preconditioned (programmed to all zeros), erased, and then verified. The read mode of the device is automatically changed to Read Status Register mode, and remains in effect until another read-mode command is issued. During a block-erase operation, STS and the Status Register indicates a busy status (SR7 = 0). Upon completion, STS and the Status Register indicates a ready status (SR7 = 1). The Status Register should be checked for any errors, then cleared. If any errors did occur, subsequent erase commands to the device are ignored unless the Status Register is cleared. The only valid commands during a block erase operation are Read Array, Read Device Information, CFI Query, and Erase Suspend. After the block-erase operation has completed, any valid command can be issued. Note: Issuing the Read Array command to the device while it is actively erasing causes subsequent reads from the device to output invalid data. Valid array data is output only after the block-erase operation has finished. Standby power levels are not be realized until the block-erase operation has finished. Also, asserting RP# aborts the block-erase operation, and array contents at the addressed location are indeterminate. The addressed block should be erased before programming within the block is attempted. 43 Datasheet www..com 9.5 Suspend and Resume An erase or programming operation can be suspended to perform other operations, and then subsequently resumed. Table 26 shows the Suspend and Resume command bus-cycles. Note: All erase and programming operations require the addressed block to remain unlocked with a valid voltage applied to VPEN throughout the suspend operation. Otherwise, the block-erase or programming operation will abort, setting the appropriate Status Register error bit(s). Also, asserting RP# aborts suspended block-erase and programming operations, rendering array contents at the addressed location(s) indeterminate. Table 26. Suspend and Resume Command Bus-Cycles Command Setup Write Cycle Address Bus Data Bus Confirm Write Cycle Address Bus Data Bus Suspend Resume Device Address Device Address 00B0h 00D0h ----- ----- To suspend an on-going erase or program operation, issue the Suspend command to any device address. The program or erase operation suspends at pre-determined points during the operation after a delay of tSUSP. Suspend is achieved when STS (in RY/BY# mode) goes high, SR[7,6] = 1 (erase-suspend) or SR[7,2] = 1 (program-suspend). Note: Issuing the Suspend command does not change the read mode of the device. The device will be in Read Status Register mode from when the erase or program command was first issued, unless the read mode was changed prior to issuing the Suspend command. Not all commands are allowed when the device is suspended. Table 27 shows which device commands are allowed during Program Suspend or Erase Suspend. Table 27. Valid Commands During Suspend (Sheet 1 of 2) Device Command Program Suspend Erase Suspend STS Configuration Read Array Read Status Register Clear Status Register Read Device Information CFI Query Word Program Buffered Program Block Erase Program Suspend Erase Suspend Program/Erase Resume Allowed Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Not Allowed Allowed Not Allowed Allowed 44 Datasheet www..com Table 27. Valid Commands During Suspend (Sheet 2 of 2) Device Command Program Suspend Erase Suspend Lock Block Unlock Block Program OTP Register Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed During Suspend, array-read operations are not allowed in blocks being erased or programmed. A block-erase under program-suspend is not allowed. However, word-program under erasesuspend is allowed, and can be suspended. This results in a simultaneous erase-suspend/ programsuspend condition, indicated by SR[7,6,2] = 1. To resume a suspended program or erase operation, issue the Resume command to any device address. The read mode of the device is automatically changed to Read Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes low, and the respective Status Register bits are cleared. When the Resume command is issued during a simultaneous erase-suspend/ program-suspend condition, the programming operation is resumed first. Upon completion of the programming operation, the Status Register should be checked for any errors, and cleared. The resume command must be issued again to complete the erase operation. Upon completion of the erase operation, the Status Register should be checked for any errors, and cleared. 9.6 Status Signal (STS) The STATUS (STS) signal can be configured to different states using the STS Configuration command. Once the STS signal has been configured, it remains in that configuration until another Configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/ BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 29 displays possible STS configurations. Table 28. STS Configuration Register Setup Write Cycle Command Address Bus Data Bus 1 Confirm Write Cycle Address Bus Data Bus 2 STS Configuration Device Address 00B8h Device Address Register Data NOTES: 1. In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address 2. In case of 256 Mb device (2x128), keep the second cycle to the same address. (ie. Do not toggle A24 for the second cycle) To reconfigure the STATUS (STS) signal to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described in the following paragraphs. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00 configuration code with the Configuration command resets the STS signal to 45 Datasheet www..com the default RY/BY# level mode. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in SR.4 and SR.5 being set. Note: STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands Table 29. STS Configuration Coding Definitions D7 D6 D5 D4 D3 D2 D1 Pulse on Program Complete (1) Notes Controls HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. Generates a system interrupt pulse when any flash device in an array has completed a block erase. Helpful for reformatting blocks after file system free space reclamation or "cleanup." Not supported on this device. Generates system interrupts to trigger servicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired. D0 Pulse on Erase Complete (1) Reserved D[1:0] = STS Configuration Codes 00 = default, level mode; device ready indication 01 = pulse on Erase Complete 10 = pulse on Program Complete 11 = pulse on Erase or Program Complete NOTES: 1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns. 2. An invalid configuration code will result in both SR4 and SR5 being set. 3. Reserved bits are invalid should be ignored. 9.7 Security and Protection Intel(R) Embedded Flash Memory (J3 v. D) device offer both hardware and software security features. Block lock operations, PRs and VPEN allow users to implement various levels of data protection. 9.7.1 Normal Block Locking J3 v. D has the unique capability of Flexible Block Locking (locked blocks remain locked upon reset or power cycle): All blocks are unlocked at the factory. Blocks can be locked individually by issuing the Set Block Lock Bit command sequence to any address within a block. Once locked, blocks remain locked when power is removed, or when the device is reset. 46 Datasheet www..com All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits command sequence to any device address. Locked blocks cannot be erased or programmed. Table 30 summarizes the command bus-cycles. Table 30. Block Locking Command Bus-Cycles Command Setup Write Cycle Address Bus Data Bus Confirm Write Cycle Address Bus Data Bus Set Block Lock Bit Clear Block Lock Bits Block Address Device Address 0060h 0060h Block Address Device Address 0001h 00D0h After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup command, the device's read mode is automatically changed to Read Status Register mode. After issuing the confirm command, completion of the operation is indicated by STS (in RY/BY# mode) going high and SR7 = 1. Blocks cannot be locked or unlocked while programming or erasing, or while the device is suspended. Reliable block lock and unlock operations occur only when VCC and VPEN are valid. When VPEN V PENLK, block lock-bits cannot be changed. When the set lock-bit operation is complete, SR4 should be checked for any error. When the clear lock-bit operation is complete, SR5 should be checked for any error. Errors bits must be cleared using the Clear Status Register command. Block lock-bit status can be determined by first issuing the Read Device Information command, and then reading from 9.7.2 Configurable Block Locking One of the unique new features on the J3 v. D, non-existent on the previous generations of this product family, is the ability to protect and/or secure the user's system by offering multiple level of securities: Non-Volatile Temporary; Non-Volatile Semi-Permanently or Non-Volatile Permanently. For additional information and collateral request, please contact your filed representative. 9.7.3 OTP Protection Registers J3 v. D includes a 128-bit Protection Register (PR) that can be used to increase the security of a system design. For example, the number contained in the PR can be used to "match" the flash component with other system components such as the CPU or ASIC, hence preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments: * One segment is programmed at the Intel factory with a unique unalterable 64-bit number. * The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming. 47 Datasheet www..com 9.7.4 Reading the OTP Protection Register The Protection Register is read in Identification Read mode. The device is switched to this mode by issuing the Read Identifier command (0090h). Once in this mode, read cycles from addresses shown in Table 31 or Table 32 retrieve the specified information. To return to Read Array mode, write the Read Array command (00FFh). 9.7.5 Programming the OTP Protection Register Protection Register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time for byte-wide configuration. First write the Protection Program Setup command, 00C0h. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Table 31, "Word-Wide Protection Register Addressing" on page 49 or Table 32, "Byte-Wide Protection Register Addressing" on page 50. See Figure 24, "Protection Register Programming Flowchart" on page 61. Any attempt to address Protection Program commands outside the defined PR address space will result in a Status Register error (SR.4 will be set). Attempting to program a locked PR segment will result in a Status Register error (SR.4 and SR.1 will be set). 9.7.6 Locking the OTP Protection Register The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program "0xFFFD" to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the Protection Register. Protection Program commands to a locked section will result in a Status Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible. Figure 15. Protection Register Memory Map Word Address 0x88 A[24:1]: 256 Mbit A[23:1]: 128 Mbit A[22:1]: 64 Mbit A[21:1]: 32 Mbit 64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0 0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-Bit Protection Register 0 64-bit Segment (Factory-Programmed) NOTE: A0 is not used in x16 mode when accessing the protection register map. See Table 31 for x16 addressing. If x8 mode A0 is used, see Table 32 for x8 addressing. 48 Datasheet www..com Table 31. Word-Wide Protection Register Addressing Word Use A8 A7 A6 A5 A4 A3 A2 A1 LOCK 0 1 2 3 4 5 6 7 Both Factory Factory Factory Factory User User User User 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.) 49 Datasheet www..com Table 32. Byte-Wide Protection Register Addressing Byte Use A8 A7 A6 A5 A4 A3 A2 A1 A0 LOCK LOCK 0 1 2 3 4 5 6 7 8 9 A B C D E F Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX:9] = 0. 9.7.7 VPP/ VPEN Protection When it's necessary to protect the entire array, global protection can be achieved using a hardware mechanism. using VPP or VPEN. Whenever a valid voltage is present on VPP or VPEN, blocks within the main flash array can be erased or programmed. By grounding VPP or VPEN, blocks within the main array cannot be altered - attempts to program or erase blocks will fail resulting in the setting of the appropriate error bit in the Status Register. By holding VPP or VPEN low, absolute write protection of all blocks in the array can be achieved. 50 Datasheet www..com Appendix A Device Command Codes For a complete definition on device operations refer to Section 8.4, "Device Commands" on page 36. The list of all applicable commands are included here one more time for the conveninece. Table 33. Command Bus Operations for J3 v. D Setup Write Cycle Command Address Bus Data Bus Address Bus Data Bus Confirm Write Cycle Program Enhanced Configuration Register Registers Register Data Device Address Device Address Device Address Device Address Device Address Device Address Device Address Device Address Word Address Device Address Device Address Device Address Block Address Block Address 0060h 00C0h 0050h 00B8h 00FFh 0070h 0090h 0098h 0040h/ 0010h 00E8h 0020h 00B0h 00D0h 0060h 0060h Register Data Register Offset ------------Device Address Device Address Block Address ----Block Address Block Address 0004h Register Data ------------Array Data 00D0h 00D0h ----0001h 00D0h Program OTP Register Clear Status Register Program STS Configuration Register Read Modes Program and Erase Security Read Array Read Status Register Read Identifier Codes (Read Device Information) CFI Query Word/Byte Program Buffered Program Block Erase Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block 51 Datasheet www..com Appendix B J3 v. D ID Codes Table 34. Read Identifier Codes Code Address Data 32-Mbit Device Code 64-Mbit 128-Mbit 00001 00001 00001 0016 0017 0018 52 Datasheet www..com Appendix C Flow Charts C.1 Write to Buffer Figure 16. Write to Buffer Flowchart Start Setup - Write 0xE8 - Block Address Check Buffer Status - Perform read operation - Read Ready Status on signal SR7 SR7 = 1? No Yes Word Count - Address = block address - Data = word count minus 1 (Valid range = 0x00 to0x1F) Load Buffer - Fill write buffer up to word count - Address = within buffer range - Data = user data Confirm - Write 0xD0 - Block address Read Status Register (SR) No SR7 = 1? Yes Full Status Register Check (if desired) End 53 Datasheet www..com C.2 Status Register Figure 17. Status Register Flowchart Start Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70 Data Cycle - Read Status Register SR[7:0] SR7 = '1' No Y es - Set/Reset by WSM SR6 = '1' Y es Erase Suspend See Suspend/Resume Flowchart No SR2 = '1' Y es Program Suspend See Suspend/Resume Flowchart No SR5 = '1' Y es SR4 = '1' Y es Error Command Sequence No No Error Erase Failure Y es SR4 = '1' Error Program Failure - Set by WSM - Reset by user - See Clear Status Register Command No SR3 = '1' Y es Error V PEN < VPENLK No SR1 = '1' Y es Error Block Locked No End 54 Datasheet www..com C.3 Byte/Word Programming Figure 18. Byte/Word Program Flowchart Start Bus Operation Write Write Command Setup Byte/ Word Program Byte/Word Program Comments Data = 40H Addr = Location to Be Programmed Data = Data to Be Programmed Addr = Location to Be Programmed Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 40H, Address Write Data and Address Read Status Register 0 1 Full Status Check if Desired Byte/Word Program Complete Read (Note 1) Standby SR.7 = 1. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Byte/Word Program Successful Programming Error Voltage Range Error Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming to Voltage Error Detect Check SR.1 1 = Device Protect Detect RP# = V IH, Block Lock-Bit Is Set Only required for systems implemeting lock-bit configuration. Check SR.4 1 = Programming Error 1 Device Protect Error Standby Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 55 Datasheet www..com C.4 Program Suspend/Resume Figure 19. Program Suspend/Resume Flowchart Start Bus Operation Write Write B0H Read Command Program Suspend Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Programming Suspended 0 = Programming Completed Read Array Data = FFH Addr = X Read array locations other than that being programmed. Program Resume Data = D0H Addr = X Read Status Register Standby 0 SR.7 = Standby Write 1 0 SR.2 = Programming Completed Write 1 Write FFH Read Read Data Array No Done Reading Yes Write D0H Write FFH Programming Resumed Read Array Data 56 Datasheet www..com C.5 Block Erase Figure 20. Block Erase Flowchart Start Bus Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note 1) Command Erase Block Erase Confirm Comments Data = 20H Addr = Block Address Data = D0H Addr = Block Address Status register data With the device enabled, OE# low updates SR Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Read Standby Write Confirm D0H Block Address 1. The Erase Confirm byte must follow Erase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Suspend Erase Loop Read Status Register No SR.7 = 0 Suspend Erase Yes 1 Full Status Check if Desired Erase Flash Block(s) Complete 57 Datasheet www..com C.6 Block Erase Suspend/Resume Figure 21. Block Erase Suspend/Resume Flowchart Bus Operation Write Write B0H Read Start Command Erase Suspend Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Read Status Register Standby 0 SR.7 = Standby Write 1 0 SR.6 = Block Erase Completed Erase Resume Data = D0H Addr = X 1 Read Read or Program? Read Array Data Done? Yes Write D0H Write FFH Program Loop Program No Block Erase Resumed Read Array Data 58 Datasheet www..com C.7 Block Locking Figure 22. Set Block Lock-Bit Flowchart Start Bus Operation Write Command Set Block Lock-Bit Setup Set Block Lock-Bit Confirm Comments Data = 60H Addr =Block Address Data = 01H Addr = Block Address Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 60H, Block Address Write 01H, Block Address Write Read Read Status Register Standby SR.7 = 1 Full Status Check if Desired 0 Repeat for subsequent lock-bit operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode. Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.4 = 0 Set Lock-Bit Successful Set Lock-Bit Error Command Sequence Error Voltage Range Error Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error Standby SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 59 Datasheet www..com C.8 Unlock Block Figure 23. Clear Lock-Bit Flowchart Start Bus Operation Write Command Clear Block Lock-Bits Setup Clear Block or Lock-Bits Confirm Comments Data = 60H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 60H Write Write D0H Read Read Status Register Standby SR.7 = 1 Full Status Check if Desired Clear Block Lock-Bits Complete 0 Write FFH after the clear lock-bits operation to place device in read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.5 = 0 Clear Block Lock-Bits Successful Clear Block Lock-Bits Error Command Sequence Error Voltage Range Error Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error Standby SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register command. If an error is detected, clear the status register before attempting retry or other error recovery. 60 Datasheet www..com C.9 OTP Protection Register Programming Figure 24. Protection Register Programming Flowchart Start Bus Operation Write Write Command Protection Program Setup Protection Program Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Standby Read Status Register SR.7 = 1? Yes Full Status Check if Desired No Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPEN Range Error 0,1 SR.1, SR.4 = Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 V PEN Low 0 0 1 Prot. Reg. Prog. Error Register Locked: Aborted 1 0 1 Protection Register Programming Error Attempted Program to Locked Register Aborted Standby SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. 1,1 SR.1, SR.4 = SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Program Successful 61 Datasheet www..com Appendix D Common Flash Interface The Common Flash Interface(CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, JEDEC ID-independent, and forwardand backward-compatible software support for the specified flash device families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. D.1 Query Structure Output The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (D[7:0]) and 00h in the high byte (D[15:8]). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. 62 Datasheet www..com Table 35. Summary of Query Structure Output as a Function of Device and Mode Device Type/ Mode Query start location in maximum device bus width addresses Query data with maximum device bus width addressing Hex Offset Hex Code ASCII Value Query data with byte addressing Hex Offset Hex Code ASCII Value x16 device x16 mode x16 device x8 mode 10h 10: 11: 12: 0051 0052 0059 N/A(1) "Q" "R" "Y" N/A(1) 20: 21: 22: 20: 21: 22: 51 00 52 51 51 52 "Q" "Null" "R" "Q" "Q" "R" NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable" for x8-configured devices. Table 36. Example of Query Structure Output of a x16- and x8-Capable Device Word Addressing Offset A15-A0 Hex Code D15-D0 Value Offset A7-A 0 Byte Addressing Hex Code D7-D0 Value 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51 51 52 52 59 59 P_IDLO P_IDLO P_IDHI ... "Q" "Q" "R" "R" "Y" "Y" PrVendor ID # ID # ... D.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail. 63 Datasheet www..com Table 37. Query Structure Offset Sub-Section Name Description Notes 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Manufacturer Code Device Code Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Block-Specific Information Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information 1 1 1,2 1 1 1 1 1,3 Command Set ID and Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 02000h is block 2's beginning location when the block size is 128 Kbyte). 3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table. D.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 38. Block Status Register Offset Length Description Address Value (BA+2)h (1) 1 BA+2: (bit 1-15): 0 NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64-KB block) beginning location in word mode). Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR 1-15: Reserved for Future Use BA+2: BA+2: --00 or --01 (bit 0): 0 or 1 D.4 CFI Query Identification String The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 39. CFI Identification (Sheet 1 of 2) Offset Length Description Add. Hex Code Value 10h 13h 15h 17h 3 2 2 2 Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 10 11: 12: 13: 14: 15: 16: 17: --51 --52 --59 --01 --00 --31 --00 --00 "Q" "R" "Y" 64 Datasheet www..com Table 39. CFI Identification (Sheet 2 of 2) Offset Length Description Add. Hex Code Value 19h 2 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists 18: 19: 1A: --00 --00 --00 D.5 System Interface Information The following device information can optimize system interface software. Table 40. System Interface Information Offset Length Description Add. Hex Code Value 1Bh 1 1Ch 1 1Dh 1 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 1 VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2n ms "n" such that typical full chip erase time-out = 2n ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2n times typical "n" such that maximum chip erase time-out = 2n times typical 1B: --27 2.7 V 1C: --36 3.6 V 1D: --00 0.0 V 1E: 1F: 20: 21: 22: 23: 24: 25: 26: --00 --06 --07 --0A --00 --02 --03 --02 --00 0.0 V 64 s 128 s 1s NA 256 s 1024 s 4s NA 65 Datasheet www..com D.6 Device Geometry Definition This field provides critical details of the flash device geometry. Table 41. Device Geometry Definition Offset Length Description Code See Table Below 27h 28h 2Ah 1 2 2 "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 27: 28: 29: 2A: 2B: --02 --00 --05 --00 x8/ x16 32 2Ch 1 2C: --01 1 2Dh 4 2D: 2E: 2F: 30: Device Geometry Definition Address 32 Mbit 64 Mbit 128 Mbit 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: --16 --02 --00 --05 --00 --01 --1F --00 --00 --02 --17 --02 --00 --05 --00 --01 --3F --00 --00 --02 --18 --02 --00 --05 --00 --01 --7F --00 --00 --02 66 Datasheet www..com D.7 Primary-Vendor Specific Extended Query Table Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 42. Primary Vendor-Specific Extended Query Offset (1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h 3 Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant Individual block locking supported bit 6 Protection bits supported bit 7 Page-mode read supported bit 8 Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block Status Register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts 1 1 (P+5)h (P+6)h (P+7)h (P+8)h 4 31: --50 32: --52 33: --49 34: --31 35: --31 36: --CE 37: --00 38: --00 39: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 1(1) bit 4 = 0 bit 5 = 0 bit 6 = 1 bit 7 = 1 bit 8 = 0 3A: --01 "P" "R" "I" "1" "1" No Yes Yes Yes(1) No No Yes Yes No (P+9)h 1 (P+A)h (P+B)h 2 bit 0 = 1 3B: --01 3C: --00 bit 0 = 1 bit 1 = 0 3D: --33 Yes Yes No 3.3 V (P+C)h 1 (P+D)h 1 3E: --00 0.0 V NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0." 67 Datasheet www..com Table 43. Protection Register Information Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value (P+E)h 1 (P+F)h (P+10)h (P+11)h (P+12)h 4 Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are userprogrammable. Bits 0-15 point to the protection register lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user-programmable bytes 3F: --01 01 40: 41: 42: 43: --80 --00 --03 --03 80h 00h 8bytes 8bytes NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h. Table 44. Burst Read Information Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value Page Mode Read capability (P+13)h 1 bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Reserved for future use 44: --03 8 byte (P+14)h 1 45: 46: --00 0 (P+15)h NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h. 68 Datasheet www..com Appendix E Additional Information Order Number Document/Tool Intel(R) StrataFlashTM Memory (J3); 28F128J3, 28F640J3, 28F320J3 Specification Update Intel(R) Persistent Storage Manager (IPSM) User's Guide Software Manual Intel(R) Flash Data Integrator (FDI) User's Guide Software Manual 5 Volt Intel(R) StrataFlashTM MemoryI28F320J5 and 28F640J5 datasheet AP-646 Common Flash Interface (CFI) and Command Sets Intel(R) Wireless Communications and Computing Package User's Guide 298130 298136 297833 290606 292204 253418 1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit the Intel home page http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel(R) Embedded Flash Memory (J3 v. D), visit http:// developer.intel.com/design/flash/isf. 69 Datasheet www..com Appendix F Ordering Information Figure 25. Decoder:Intel(R) Embedded Flash Memory (J3 v. D) Family P C2 8 F 3 2 0 J 3 D - 7 5 Package TE= 56-Lead TSOP (J3C, 803) JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA PC = 64-Ball Pb-Free Easy BGA Access Speed 75 ns D = Intel(R) 0.13 micron lithography Voltage (Vcc/VPEN) 3 = 3 V/3 V Product Family J = Intel(R) Embedded Flash Memory Product line designator For all Intel(R) Flash Products Device Density 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Table 45. Order Information: Intel(R) Embedded Flash Memory (J3 v. D) Family 56-Lead TSOP 64-Ball Easy BGA TE28F128J3D-75 TE28F640J3D-75 TE28F320J3D-75 JS28F128J3D-75 JS28F640J3D-75 JS28F320J3D-75 RC28F128J3D-75 RC28F640J3D-75 RC28F320J3D-75 PC28F128J3D-75 PC28F640J3D-75 PC28F320J3D-75 70 Datasheet www..com 1.0 1.1 1.2 1.3 Introduction.............................................................................................................6 Nomenclature .................................................................................................. 6 Acronyms ........................................................................................................ 6 Conventions .................................................................................................... 6 2.0 2.1 2.2 Functional Overview............................................................................................8 Block Diagram ............................................................................................... 10 Memory Map ................................................................................................. 11 3.0 3.1 3.2 Package Information ......................................................................................... 12 56-Lead TSOP Package ............................................................................... 12 Easy BGA Package....................................................................................... 13 4.0 4.1 4.2 4.3 Ballouts and Signal Descriptions.................................................................15 Easy BGA Ballout (32/64/128 Mbit)............................................................... 15 56-Lead TSOP Package Pinout (32/64/128 Mbit) ......................................... 16 Signal Descriptions........................................................................................ 17 5.0 5.1 5.2 5.3 Maximum Ratings and Operating Conditions.........................................19 Absolute Maximum Ratings........................................................................... 19 Operating Conditions..................................................................................... 19 Power Up/Down ............................................................................................ 20 5.3.1 Power-Up/Down Characteristics ...................................................... 20 5.3.2 Power Supply Decoupling ................................................................ 20 Reset ............................................................................................................. 20 5.4 6.0 6.1 6.2 6.3 Electrical Characteristics ................................................................................ 21 DC Current Specifications ............................................................................. 21 DC Voltage specifications ............................................................................. 22 Capacitance .................................................................................................. 23 7.0 7.1 7.2 7.3 7.4 7.5 AC Characteristics ............................................................................................. 24 Read Specifications....................................................................................... 25 Write Specifications....................................................................................... 28 Program, Erase, Block-Lock Specifications .................................................. 30 Reset Specifications ...................................................................................... 31 AC Test Conditions ....................................................................................... 32 8.0 8.1 Bus Interface.........................................................................................................33 Bus Reads..................................................................................................... 34 8.1.1 Asynchronous Page Mode Read...................................................... 34 8.1.1.1 Enhanced Configuration Register (ECR) ............................ 34 8.1.2 Output Disable.................................................................................. 35 Bus Writes ..................................................................................................... 35 Standby ......................................................................................................... 36 8.3.1 Reset/Power-Down .......................................................................... 36 Device Commands ........................................................................................ 36 8.2 8.3 8.4 9.0 9.1 Flash Operations.................................................................................................38 Status Register.............................................................................................. 38 9.1.1 Clearing the Status Register ............................................................ 39 i Datasheet www..com 9.2 9.3 9.4 9.5 9.6 9.7 Read Operations ............................................................................................39 9.2.1 Read Array ........................................................................................39 9.2.2 Read Status Register ........................................................................40 9.2.3 Read Device Information...................................................................40 9.2.4 CFI Query..........................................................................................41 Programming Operations ...............................................................................41 9.3.1 Single-Word/Byte Programming........................................................41 9.3.2 Buffered Programming ......................................................................42 Block Erase Operations .................................................................................43 Suspend and Resume....................................................................................44 Status Signal (STS)........................................................................................45 Security and Protection ..................................................................................46 9.7.1 Normal Block Locking .......................................................................46 9.7.2 Configurable Block Locking...............................................................47 9.7.3 OTP Protection Registers .................................................................47 9.7.4 Reading the OTP Protection Register ...............................................48 9.7.5 Programming the OTP Protection Register.......................................48 9.7.6 Locking the OTP Protection Register ................................................48 9.7.7 VPP/ VPEN Protection ......................................................................50 Appendix A Appendix B Appendix C Device Command Codes ................................................................................. 51 J3 v. D ID Codes .................................................................................................. 52 Flow Charts ........................................................................................................... 53 Write to Buffer ................................................................................................53 Status Register...............................................................................................54 Byte/Word Programming ................................................................................55 Program Suspend/Resume ............................................................................56 Block Erase ....................................................................................................57 Block Erase Suspend/Resume ......................................................................58 Block Locking .................................................................................................59 Unlock Block ..................................................................................................60 OTP Protection Register Programming..........................................................61 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Appendix D Common Flash Interface ................................................................................. 62 Query Structure Overview ..............................................................................63 Block Status Register .....................................................................................64 CFI Query Identification String .......................................................................64 System Interface Information .........................................................................65 Device Geometry Definition ...........................................................................66 Primary-Vendor Specific Extended Query Table ...........................................67 D.2 D.3 D.4 D.5 D.6 D.7 Appendix E Appendix F Additional Information...................................................................................... 69 Ordering Information.........................................................................................70 ii Datasheet |
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